STM32 H563 I2C TIMINGR Add
Description
Description
The STM32H5 series (e.g., STM32H563/H573) features high-performance I2C peripherals (I2C V2 IP), which utilize the 32-bit I2C_TIMINGR register for baud rate and timing configuration (Standard-mode, Fast-mode, and Fast-mode Plus).
Currently, in ports/stm32/, the preprocessor logic for I2C_V2 and TIMINGR calculation includes families like STM32H7, STM32G0/G4, and STM32WB, but STM32H5 is notably absent. This prevents the driver from correctly initializing the I2C block on H5 hardware.
Verification & Results
I have implemented a patch to include STM32H5 in the I2C V2 logic. Local testing on a H563RI Board demonstrates that the timing calculation is accurate. I have successfully verified stable I2C communication at standard bus speeds, as well as custom configurations up to 1.5 MHz (overclocked Fast-mode Plus), which confirms the flexibility and correctness of the timing logic.
<img width="586" height="292" alt="Image" src="https://github.com/user-attachments/assets/e14a14fe-a3df-4fdb-9b7a-838631271579" />
Code Size
No response
Implementation
I hope the MicroPython maintainers or community will implement this feature
Code of Conduct
Yes, I agree
stm32/i2c: Add hardware I2C implementation for STM32L4.
For STM32L4, hardware I2C can implement by using TIMINGR.
This PR makes to be able to:
- Use of hardware I2C in machine.I2C.
- Specify frequency greater than or equal to 400KHz with pyb.I2C.
In pyb_i2c.c, TIMINGR for STM32L4 is defined as:
https://github.com/micropython/micropython/blob/68f166dae9ad6dfd94038d5f4394defbb44238af/ports/stm32/pyb_i2c.c#L209-L216
but according to STM32CubeIDE, the value of TIMINGR for standard mode is the same with NUCLEO-476RG and STM32L476G-Discovery.
So it can be replaced with the value genereted by STM32CubeIDE.
Tested on NUCLEO-L476RG.