QUERY · ISSUE

Enhancement: please add support for the ADR assembler opcode

openby IowaDaveopened 2020-01-06updated 2020-01-07

Please add support for the ADR opcode in micropython for microbit. We need to utilize a temporary data table inside an assembler def.

Using 'adr' gives an error something like: "unsupported Thumb command 'adr' "

Desired usage:

def example():
    b(LABEL1)
    label(LABEL2)
    data(4, 1, 2, 3, 4, 5, 6, 7, 8)
    label(LABEL1)
    adr(r1, LABEL2) # r1 =  address of where data starts
# or, this is how it appears in some ARM/Thumb documentation:
#  adr(r0,=LABEL2) # r1 = address of LABEL2
    ldr(r0, [r1, 0]) # return value pointed to by LABEL2

If adr opcode cannot be supported, then please suggest a workaround using available opcodes. Thank you!

CANDIDATE · PULL REQUEST

py/asmrv32: Add support for RV32 Zba opcodes.

mergedby agattiopened 2025-07-07updated 2025-09-21

py-core

Summary

This PR adds support for RV32 Zba address generation opcodes to several places in MicroPython (scaled addition operation used for calculating halfword and word offsets):

the native emitter will emit Zba opcodes if configured to do so for Viper/Native 16- and 32-bits register-indexed load/store operations
the inline assembler is now able to emit SH1ADD, SH2ADD, and SH3ADD opcodes
the rp2 port will emit Zba opcodes at runtime for RP2350 firmwares when built using the RISCV variant
mpy-cross now has an extra implementation-dependent option to enable generation of Zba opcodes when pre-compiling native or viper code into a MPY file

~~With these changes, each load/store operation that can use these opcodes will be 2 bytes shorter.~~

With these changes, all non-byte load/store operations have been shortened by two bytes, and operations that can use these opcodes will be one instruction shorter (fewer CPU cycles and fewer register stalls).

Testing

The inline assembler changes were tested on QEMU (to check they work), and on an ESP32C3 (to check whether the appropriate tests are skipped if those opcodes are not supported).

Runtime changes were tested on QEMU, built with and without MICROPY_EMIT_RV32_ZBA being set, running the full RV32 test suite.

mpy-cross changes were tested by looking at the emitted output code of viper ptr tests through a disassembler; both with and without -X riscv=zba in mpy-cross command line.

Trade-offs and Alternatives

There's a fixed 4 bytes (or 8 bytes on 64 bit targets) RAM overhead to let the dynamic compiler settings structure hold a pointer to an emitter-specific options structure.

This mechanism, in theory, could lead to the deprecation of the various Armv7 sub-types, as they could be command line switches instead.